Last modified on 2 August 2009, at 04:56

Talk:assert

  • Discussion
Return to "assert" page.

In electronic (and software) engineering, variables are "asserted". This usually means they are made logical true, 1 (as opposed to 0), or in electronics, to a +ve voltage.

However, the subtlety of the use of assert can be as follows: the signal RESET might be +ve voltage at all times, and only be 0v when the system is to be reset. The statement "the reset line went low" is colloquially true, but counter-intuitive. The statement "the resent line was asserted" makes much more sense, and is thus used.

This use of the word does not appear in the definition currently - can anyone help in the phrasing?

I had a shot. Change it if you think it's necessary, and add an example if possible.Gregcaletta 04:56, 2 August 2009 (UTC)